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Faculty Profile

Dr. Tresa Joseph

Assistant Professor

Dr. Tresa Joseph, Assistant Professor in the Department of Electronics and Biomedical Engineering at ASIET since January 2024, holds a Ph.D. in low-power VLSI architectures for Neural Networks from NIT Calicut. She also holds an M.Tech from MG University (2013) and a Bachelor's degree in Electronics and Communication Engineering from Calicut University (2011).

With a strong academic and research foundation in Electronics and Communications Engineering, Dr. Tresa Joseph specializes in advanced chip design, VLSI, RTL coding, and low-power AI hardware architectures. A published author and accomplished VLSI researcher, she is currently transitioning into roles focused on logic and physical design, bringing her academic insights into dynamic industry applications.

She is proficient in industry-standard platforms such as Cadence Genus, Innovus, and Verilog, and continues to contribute significantly to the field of low-power VLSI and AI hardware systems.

Qualification details

DEGREE	UNIVERSITY	YEAR
B.Tech	CALICUT UNIVERSITY	2011
M.Tech	MG UNIVERSITY	2013
Ph.D	NIT CALICUT	2024

Journal Articles

1. T. Joseph and T. Bindiya, “Performance-driven lstm accelerator hardware using split-matrix-based mvm circuits, systems, and signal processing,” in Springer, pp. 1–24, 2023. doi: 10.1007/s00034-023-02412-4.

2 T. Joseph and T. Bindiya, “Power and delay-efficient matrix vector multiplier units for the lstm networks using activity span reduction technique and recursive adders. circuits, systems, and signal processing,” in Springer, pp. 1–35, 2023. doi: 10.1007/s00034-023-02456-6.

3 T. Joseph and T. Bindiya, “Power efficient realization of gating units in the lstm networks.,” Computers and Electrical Engineering (under review), 2023.

4 T. Joseph and T. Bindiya, “Real-time blood pressure prediction on wearable devices using edge based deep neural networks: A hardware-software co-design approach,” ACM Transactions on Design Automation of Electronic Systems (under review), 2023.

5 T. Joseph and T. Bindiya, “Realization and hardware implementation of gating units for long short term memory network using hyperbolic sine function,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1–5, 2023. doi: 10.1109/TCAD.2023.3293045.

6 T. j. Mrinmay Sasmal and B. T. S., “Design of approximate multipliers using lfsr based stochastic sequence generators for edge-based ai applications.,” IEEE Computer Architectural Letters (under review), 2023.

Conference Proceedings

1.T. Joseph and T. Bindiya, “High speed and power efficient multiplexer based matrix vector multiplication for lstm network,” in IEEE-2021 25th International Symposium on VLSI Design and Test (VDAT), Sep 16, 2021. doi: 10.1109/vdat53777.2021.9601075.

2 T. Joseph and et.al, “Hardware realization of sigmoid and hyperbolic tangent activation functions,” in The 2022 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT), Jul 28, 2022. doi: 10.1109/iaict55358.2022.9887382.

3 J. A. Teffi Francis and T. Joseph, “Modified mac unit for low power high speed dsp application using multipler with bypassing technique and optimized adders,” in In IEEE 2013 fourth international conference on computing, communications and networking technologies (ICCCNT), Jul 4, 2013, pp. 1–4. doi: 10.1109/ICCCNT.2013.6726839.